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Company News

  • 2019-04-01 We are hiring! Check out our job offering now=> read more
  • 2019-03-18 NetTimeLogic will be at the FPGA Kongress 2019 in Munich, Germany May 21st - May 23rd and will have a presentation about TSN => read more
  • 2019-02-22 NetTimeLogic will take part in the IIC TSN Testbed Plugfest in Stuttgart, Germany on March 5th -  March 8th => test with us
  • 2019-02-15 NetTimeLogic will held a free PTP seminar in Switzerland together with Mobatime and Albedo for everybody interested in PTP or network synchronization in general => register now
  • 2019-01-14 NetTimeLogic announces its 10G PTP OC for Q1 2019
  • 2019-01-01 NetTimeLogic wishes everybody a Happy New Year!
  • 2018-09-10 NetTimeLogic released its first Time Sensitive Networking IP core: TSN Network Node => read more
  • 2018-08-27 The IRIG cores (Master and Slave) from NetTimeLogic now support IRIG-B with AC encoding and amplitude modulation (IRIG-B120 - IRIG-B127) with an accuracy better than 1 us=> read more
  • 2018-07-23 NetTimeLogic is proud sponsor of the TSNA 2018 conference on Sep. 26th & 27th in Stuttgart, Germany. Get the latest news about Time Sensitive Networking and don't forget to visit us at our sponsor booth and talk with us about our TSN solution => read more
  • 2018-06-21 The PPS Analyzer now supports logging of measurements. This allows to trace the accuracy even for a very long time => read more
  • 2018-06-20 NetTimeLogic announces its latest core: DCF Master => read more
  • 2018-05-23 NetTimeLogic proudly announces that it is now a Xilinx Alliance Program Member => read more
  • 2018-04-25 NetTimeLogic joined the HardwareBee network => read more
  • 2018-02-14 NetTimeLogic will attend Embedded World 2018 in Nuernberg Germany: February 28th - March 1st
  • 2017-12-28 NetTimeLogic announce DCF Products, in particular a DCF Slave which can synchronize to the DCF77 sender near Frankfurt, Germany with an accuracy better than one millisecond => read more
  • 2017-11-14 NetTimeLogic developed and provides a PPS Analyzer device for the swiss PTP Plugfest =>  read more
  • 2017-10-03 NetTimeLogic is proud organizer and sponsor of the first swiss PTP Plugfest in Winterthur => read more
  • 2017-09-12 Successful testing of our cores at ISPCS2017, NetTimeLogic introduced the "ISPCS proved" logo for all the cores tested sucessfuly at ISPCS => read more
  • 2017-08-18 PTP Tap beta version released => read more
  • 2017-07-19 HSR/PRP Manual released => read more
  • 2017-06-16 HSR/PRP released => read more
  • 2017-04-01 NetTimeLogic is proud Silver sponsor of ISPCS2017 in Monterey => read more
  • 2017-03-18 NMEA Master released => read more
  • 2017-03-14 NetTimeLogic at Embedded World in Nurnberg
  • 2017-02-10 Pricing of allour products updated
  • 2017-01-06 RTC Master Clock released => read more
  • 2016-12-28 Free Configuration Tool beta release => read more
  • 2016-12-08 NetTimeLogic announces Real Time Clock (RTC) Master core allowing to read and write RTC clocks via I2C without time format conversion. Clock accuracy in the range of +/- 100 ns is achieved. This allows storing and recovering time from a non volatile storage => read more2016-11-09 IRIG-B Master and Slave released => read more
  • 2016-10-28 IRIG-B up and running andsynchronizing accurate to +/-20 ns2016-10-27 NetTimeLogic moved the Headquarter to it's new office
  • 2016-09-04 NetTimeLogic is testing and presenting at the ISPCS2016
  • 2016-08-25 First redundant PTP node ready for beta testing
  • 2016-08-24 NetTimeLogic is partnering with Enclustra GmbH, not only will we share our expertise but also we will use Enclustra's Mars series AX3/PM3 hardware for additional reference designs => read more
  • 2016-08-12 NetFPGA CML was added as a new reference hardware for NetTimeLogics IP cores
  • 2016-08-09 Added Reference Manuals to website for some of the cores
  • 2016-05-06 NetTimeLogic is proud sponsor of ISPCS2016 in Stockholm => read more
  • 2015-04-27 Added network redudndancy cores to NetTimeLogics products => read more
  • 2016-02-28 Website update for multiple cores, adapted pricing, discounts and licensing
  • 2016-01-29 Reference designs for PTP OC/TC/HC/GM and PPS Master/Slave created for Altera's SoCkit and Xilinx Arty development boards, free demo donwloads will follow soon >> read more
  • 2016-01-10 PPS Master and Slave implemented and tested >> read more
  • 2015-10-14 NetTimeLogic succesfully tested OC/TC/HC at ISPCS2015 in Beijing >> read more
  • 2015-10-11 NetTimeLogic attended ISPCS2015 in Beijing
  • 2015-09-11 Flyers of PTP OC, TC and HC added.
  • 2015-09-10 NetTimeLogic will take part in the Industrial Day of the ISPCS >> read more
  • 2015-07-09 NetTimeLogic will take part in the ISPCS Plufest in Beijing to verify PTP cores. >> read more
  • 2015-06-11 NetTimeLogic is part of "Swiss Made Software". >> read more

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IRIG-B12x with DAC and ADC

NetTimeLogic just released the AC amplitude modulated versions of its IRIG Master and IRIG Slave IP cores and we will give you some insight to our solution. In this post we want to explain how high accuracy (<2 us) IRIG-B12x (sine wave encoded, amplitude modulated IRIG-B) can be implemented using cheap DACs and ADCs.

As with all NetTimeLogic IP cores this is also an FPGA only solution (no software required), however some aditional Analog/Digital converter chips are required. The goal of this solution is to get highest accuracy synchronization, with minimal costs.

The solution is using external DACs (Digital to Anlog Converter, Digilent PmodDA2) and ADCs (Analog to Digital Converter, Digilent PmodAD1) for the handling of the analog sine wave of IRIG-B12X.

This is how our setup looks like: We use two Digilent ArtyA7-100 for our development, one is acting as an IRIG Master (with the DAC), the other is acting as an IRIG Slave (with the ADC) and we are comparing the PPS (Pulse Per Second) from the two counter clocks which are synchronized via IRIG-B127

The PmodDA2 module is a Digital to Analog Converter board from Digilent in a PMOD format featuring a Texas Instruments DAC121S101 DAC which is a 12bit DAC with a maximum sample rate of 1 mega sample per second and a SPI like interface.

The PmodAD1 module is a Analog to Digital Converter board from Digilent in a PMOD format featuring a Analog Devices AD7476A ADC which is a 12bit ADC with a maximum sample rate of 1 mega sample per second and a SPI like interface.

The sine wave encoding and decoding as well as the ADC and DAC controllers are completly independent modules in the FPGA.

On the DAC side, the encoder takes a DCLS (DC level shift) IRIG-B signal comming from the NetTimeLogic IRIG Master and converts it into an aligned (with the local counter clock) sine wave signal as samples of N bits (configurable depending on the DAC) with a modulated amplitude for 0/1 encoding for the DAC. The number of samples per sine wave period and bits per sample are configurable to allow all kind of DACs. The amplitude is encoded in a way that it uses the full DAC range for a logic one and 1/3 of the amplitude for a logic zero. Then a simple SPI controller is triggered for each sample which it then feeds to the DAC over a SPI like interface at 12.5MHz. With this setup a sample rate of 500kHz (based on the counter clock) is used.

The picture below shows how the IRIG-B00x signal is aligned with the generated IRIG-B12x signal. Amplitude changes happen at the level change of the DC signal. The analog signal is sligtly shifted by the DAC delay for the convertion and the SPI access. This delay can be configured in the NetTimeLogic IRIG Master as output delay and will be compensated accordingly, so the sine wave is perfectly aligned with the counter clock.

On the ADC side, a simple SPI controller reads the voltage value from the ADC via an SPI like interface every 2 us (based on the local clock) which equals to a sample rate of 500kHz. These samples are then feed to the decoder. The decoder does an automatic signal, offset, range and zero crossing detection and converts the sine wave samples into a DCLS IRIG-B signal which is then feed as input to the NetTimeLogic IRIG Slave.

The picture below shows how the IRIG-B12x signal is aligned with the decoded IRIG-B00x signal. DCLS changes happen ¼ of a sine wave period after the zero crossing of the sine wave (at the first positive peak after the zero crossing). This because this is the first deterministic point where the amplitude can be checked to determine if a zero or one was modulated. This constant offset is no issue, since in the NetTimeLogic IRIG Slave this value can be configured as input delay and will be compensated for accordingly. Additionaly the ADC delay for the convertion and reading over SPI shall be added to the input delay to achive high accuracy synchronization without offset.

The synchronization accuracy can be checked by comparing the PPS of the two modules which are feed to a pin. A rising edge marks the beginning of a new second on the counter clock.

With the setup described above a synchronization accuracy of less than 1.5us can be achieved.

For more information check

Update: After some fine tuning of the servo parameters the accuracy has improved to less than +/- 800ns. Since the detection of the zero crossing higly depends on the accuracy of the ADC, noise and the sampling rate, differnet PI servo paramters were choosen to make it slower and filtering out this sources of inaccuracy.

Posted 38 weeks ago