DCF Master

NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via DCF signal encoded as PWM over a cable. The core encodes the time in the same format as the DCF77 sender, so it is compatible with DCF77 nodes which use the PWM encoded DCLS signal (which is what comes normaly from a DCF77 receiver). The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

Block Diagram

DCF Master

Data Stream

Data Stream aligned with PPS for distribution over a cable


  • DCF MasterClock
  • Supports DCF-77 format
  • DCF encoding and time format conversion
  • Output delay compensation
  • Additional seconds correction to convert between UTC and TAI time (or any other time base)
  • Synchronization accuracy: +/- 10 ms
  • AXI4 Light register set or static configuration
  • Timestamp resolution with 50 MHz system clock: 20ns

Licensing & Pricing

There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  3100$
  • Site Source Code: 5600$

All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.


Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access

Dcf_Master_Flyer.pdf Dcf_Master_Flyer.pdf
Size : 112.902 Kb
Type : pdf
Dcf_Master_ReferenceManual.pdf Dcf_Master_ReferenceManual.pdf
Size : 611.128 Kb
Type : pdf