Home

Welcome to NetTimeLogic, your partner for FPGA vendor independent time synchronization and high availability real-time network solutions.
We offer swiss quality engineering - highest quality, always on time!

Products

With our product portfolio we can offer complete time and frequency synchronization, network redundancy and time sensitive networking solutions which can be tailored to your needs.

We offer low foot print FPGA-only PTP, NTP, PPS, IRIG, GPS, TOD, RTC, DCF, SyncE and Clock synchronization cores as well as HSR and PRP network redundancy and TSN IP cores.

read more

And we offer our unique Hardware platform AIONYX, specifically designed for synchronization and networking applications.

read more

Services

We also offer design services in the field of FPGA and Embedded Software development.

With our 15+ years of experience and certification in FPGA and software development as well as product and project management we bring in our expertise to design the best possible solution for you.

We understand your needs and can give you support to develop a best in class product.

read more

Tools

For all our products we provide a free of charge configuration tool which allows you to quickly configure and supervise the status of the cores.
In addition we provide tools for testing, analysis and debuging of synchronization and TSN.

read more

Company

NetTimeLogic is your partner for synchronization, network redundancy and time sensitive networking solutions in the field of embedded systems since 2015. With our expertise in all kind of synchronization and redundancy protocols, FPGA and software development we can offer you out-of-the-box synchronization, network redundancy and time sensitive networking products or customized solutions.

read more

Latest News

  • 2024-10-25 We are progressing fast with our AIONYX platform and just announced two System-Level products combining our AIONYX HW Modules and field proven IP Cores: AIONYX Hive-S and AIONYX-Hive-M => read more
  • 2024-10-01 The development on AIONYX just made some big steps: The highly customizable base designs are ready. This allows to easily create different FPGA images in just a matter of minutes. In addition our newly developed Universal Web Manager (UWM) is a web based configuration tool for our AIONYX Main Platform
  • 2024-10-01 The latest PPS Analyzer Firmware and GUI are available for download. It contains histogramm and ADEV calulations and many small improvments
  • 2024-09-13 Many new features released on the PPS Analyzer
  • 2024-08-03 The AIONYX Platform is growing by many new modules, like PM ETH, PM GPIO RAW, etc.
  • 2024-04-17 After TDC follows DTC. Which means we can now generate signals with 1ns Accury with our PPS Master, Signal Generator and Frequency Generator IP cores
  • 2024-04-05 We just added 1ns AccuracyTimestamping using TDC to our PPS Slave and Signal Timestamping IP cores => read more
  • 2024-03-22 We just added support for the ESIP protocol for Furuno GNSS receivers to our TOD Slave IP core => read more
  • 2024-03-08 Our full hardware PTP Client and Server prototypes based on the FlashPTP specification from Meinberg are up and running! We believe this is one of the next big steps in time synchronization. Once standardized as CSPTP it might be the replacement for the good old NTP... => read more
  • 2024-02-21 We just added IPv6 support to our NTP products (both NTP Server and Client)
  • 2024-02-09 NetTimeLogic just released yet another add-on core: a Clock to Pulse Per Second (PPS) Generator, allowing any input frequency between 100Hz and 100MHz (runtime configurable) and generating a PPS of configurable duty cycle and polarity. This can be used to synchronize to external frequencies via a PPS Slave or can also be used in combination with SyncE if the clock shall be nummerically controlled => read more
  • 2024-01-23 NetTimeLogic just released its latest add-on core: a SyncE Node for ESMC and Enhanced ESMC frame handling and state decision => read more
  • 2024-01-05 Our latest Open Compute Project (OCP) contribution got published. NetTimeLogic contributes to OCP in the support of OCP-Time Appliances Project (OCP-TAP) where NetTimeLogic has implemented the whole FPGA Design for the TimeCard.
  • 2023-11-08 We are glad to announce that Kevin Schärer joined the NetTimeLogic team after his internship a couple of months back. He will work as a hardware, software and FPGA design engineer at NetTimeLogic. Stay tuned for a lot of new AIONYX Pmod™ compatible Modulesto come!
  • 2023-10-24 Less than one week to go to unveil AIONYX at ITSF2023
  • 2023-08-22 NetTimeLogic just released its add-on core to our Adjustable Clock IP Core: a Frequency Converter to adapt the calculated frequency directly on a SiTime Oscillator via I2C instead of numerically => read more

see all news

Upcoming Events

 NetTimeLogic will be again a Gold Sponsor at the ITSF 2024 taking place November 4th - 7th, 2024 in Seville, Spain. We also will have a presentation on the main stage about Timing capabilities of CPUs/MCUs/FPGAs => read more

Past Events

NetTimeLogic will be again a Silver Sponsor at the ISPCS2024 taking place October 7th -11th, 2024 in Tokyo, Japan.
We will have two presentations and are also part of the Plugfest Comittee which is an essential part of ISPCS testing interoperability of PTP devices => read more

NetTimeLogic will be at the TSN/A 2024 which took place October 1st - 2nd, 2024 in Stuttgart, Germany => read more