Welcome to NetTimeLogic, your partner for FPGA vendor independent time synchronization and high availability real-time network solutions.
We offer swiss quality engineering - highest quality, always on time!
With our product portfolio we can offer complete time and frequency synchronization, network redundancy and time sensitive networking solutions which can be tailored to your needs.
We offer low foot print FPGA-only PTP, NTP, PPS, IRIG, GPS, TOD, RTC, DCF, SyncE and Clock synchronization cores as well as HSR and PRP network redundancy and TSN cores.
Also we offer Tools and some Hardware related to our products.
We also offer design services in the field of FPGA and Embedded Software development.
With our 15+ years of experience and certification in FPGA and software development as well as product and project management we bring in our expertise to design the best possible solution for you.
We understand your needs and can give you support to develop a best in class product.
For all our products we provide a free of charge configuration tool which allows you to quickly configure and supervise the status of the cores.
In addition we provide tools, for testing, analysis and debuging of synchronization and TSN.
NetTimeLogic is your partner for synchronization, network redundancy and time sensitive networking solutions in the field of embedded systems since 2015. With our expertise in all kind of synchronization and redundancy protocols, FPGA and software development we can offer you out-of-the-box synchronization, network redundancy and time sensitive networking products or customized solutions.
- 2024-02-21 We just added IPv6 support to our NTP products (both NTP Server and Client)
- 2024-02-09 NetTimeLogic just released yet another add-on core: a Clock to Pulse Per Second (PPS) Generator, allowing any input frequency between 100Hz and 100MHz (runtime configurable) and generating a PPS of configurable duty cycle and polarity. This can be used to synchronize to external frequencies via a PPS Slave or can also be used in combination with SyncE if the clock shall be nummerically controlled => read more
- 2024-01-23 NetTimeLogic just released its latest add-on core: a SyncE Node for ESMC and Enhanced ESMC frame handling and state decision => read more
- 2024-01-05 Our latest Open Compute Project (OCP) contribution got published. NetTimeLogic contributes to OCP in the support of OCP-Time Appliances Project (OCP-TAP) where NetTimeLogic has implemented the whole FPGA Design for the TimeCard.
- 2023-11-08 We are glad to announce that Kevin Schärer joined the NetTimeLogic team after his internship a couple of months back. He will work as a hardware, software and FPGA design engineer at NetTimeLogic. Stay tuned for a lot of new AIONYX PMODs to come!
- 2023-10-24 Less than one week to go to unveil AIONYX at ITSF2023
- 2023-08-22 NetTimeLogic just released its add-on core to our Adjustable Clock IP Core: a Frequency Converter to adapt the calculated frequency directly on a SiTime Oscillator via I2C instead of numerically => read more
- 2023-04-20 NetTimeLogic just released its newest IP core: a source synchronous Frequency Generator for any frequency between 1Hz and 10MHz in 1 Hz steps => read more
NetTimeLogic will again take part in the IIC TSN Testbed taking place Q1 2024 (date tbd) at the ISW in Stuttgart, Germany. We not only do interop tests there but also provide essential test equipment to the testbed => read an article about a previous pugfest at the IIC Testbed
NetTimeLogic has been a Gold Sponsor at the ITSF 2023 which took place October 31st - November 2nd, 2023 in Antwerb, Belgium. Wealso had a presentation on the main stage about Redundant Network Synchronization Schemes => read more
NetTimeLogic did again take part in the IIC TSN Testbed taking place October 17th -20th, 2023 at the ISW in Stuttgart, Germany. We not only did interop tests there but also provide essential test equipment to the testbed and did tests of our ITU unicast profile implementations with Calnex=> read an article about a previous pugfest at the IIC Testbed