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  • 2020-08-21 Due to the lasting Corona/Covid19 situation we are sad to announce, that we need to postpone the second PTP workshop which should have taken place in Sumiswald on the 16th of September 2020. The new workshop date is not yet defined, stay tuned for the announcement of the new date. Hope to see you there.
  • 2020-07-09 NetTimeLogic will do a webinar on TSN on the 24th of September 2020 together with Arrow => read more and register today
  • 2020-07-09 NetTimeLogic will do a second workshop on PTP on the 16th of September 2020 in Sumiswald, Switzerland together with Mobatime and Albedo Telecom, this time its all about PTP in the power industry, and how PTP works together with network redundancy concepts like HSR or PRP => read more and register today
  • 2020-07-09 NetTimeLogic's PPS Analyzer now supports Ethernet to connect and multi user access => read more
  • 2020-05-27 NetTimeLogic moved its headquarter from Raeffelstrasse 24 to Binzstrasse 23. This is only about 100m away from the old location and still inthe Binz area of Zurich (8045 Zurich) => check out our new location under contacts
  • 2020-03-24 Today NetTimeLogic celebrates its 5th anniversary! Thanks to everyone who supported us in the last 5 years and we are looking forward to the next 5 years of interesting projects and new IP cores to come!
  • 2020-03-12 We just released our latest revision of our PPS Analyzer Schield, and it's now for sale! => read more
  • 2020-02-03 NetTimelogic just ported it's TSN End Node IP core to the Trenz Intel/Altera Cyclone 10 LP Ref Kit
  • 2020-02-03 NetTimelogic joined the Design&Reuse Partner program (, we will start listing all our cores also there in the next days => read more
  • 2020-01-07 NetTimeLogic joins Digi-Key's Design & Integration Services program => read more
  • 2019-10-03 We hope to see you all at the TSN/A Oct. 8th - Oct. 9th, 2019 at Bad Homburg (Near Frankfurt), Germany. You will have the chance to talk to us about our TSN solutions and see them live in action => read more
  • 2019-09-10 First release of our TSN End Node solution => read more
  • 2019-08-30 Check out our latestblog post about how to port OPC-UA on a Xilinx FPGA using MicroBlaze, FreeRTOS, LwIP and Open62541 => read more
  • 2019-08-01 We are happy to announce that NetTimeLogic has extended its workfoce with Thomas Schaub as a principal FPGA Design Engineer => read more
  • 2019-07-08 NetTimeLogic will be at ECC2019: Sep. 3rd, 2019 at Winterthur, Switzerland and we will have a presentation about TSN and we will show our TSN solution. Visit us and see out cores live  => read more
  • 2019-06-28 NetTimeLogic will be at TSNA2019: Oct. 8th - Oct. 9th, 2019 at Bad Homburg (Near Frankfurt), Germany and will show it TSN solution. Visit us and see out cores live => read more
  • 2019-04-30 We are happy to announce our IIC(R) TSN Testbed/Plugfest companion core for our TSN solutions. It handles OPC/UA real-time frames in hardware as a Talker, Listener, Analyzer and Publisher as well as implements the LED application defined by the IIC(R) Testbed => read more
  • 2019-04-01 We are hiring! Check out our job offering now=> read more
  • 2019-03-18 NetTimeLogic will be at the FPGA Kongress 2019 in Munich, Germany May 21st - May 23rd and will have a presentation about TSN => read more
  • 2019-02-22 NetTimeLogic will take part in the IIC TSN Testbed Plugfest in Stuttgart, Germany on March 5th -  March 8th => test with us
  • 2019-02-15 NetTimeLogic will held a free PTP seminar in Switzerland together with Mobatime and Albedo for everybody interested in PTP or network synchronization in general => register now
  • 2019-01-14 NetTimeLogic announces its 10G PTP OC for Q1 2019
  • 2019-01-01 NetTimeLogic wishes everybody a Happy New Year!
  • 2018-09-10 NetTimeLogic released its first Time Sensitive Networking IP core: TSN Network Node => read more
  • 2018-08-27 The IRIG cores (Master and Slave) from NetTimeLogic now support IRIG-B with AC encoding and amplitude modulation (IRIG-B120 - IRIG-B127) with an accuracy better than 1 us=> read more
  • 2018-07-23 NetTimeLogic is proud sponsor of the TSNA 2018 conference on Sep. 26th & 27th in Stuttgart, Germany. Get the latest news about Time Sensitive Networking and don't forget to visit us at our sponsor booth and talk with us about our TSN solution => read more
  • 2018-06-21 The PPS Analyzer now supports logging of measurements. This allows to trace the accuracy even for a very long time => read more
  • 2018-06-20 NetTimeLogic announces its latest core: DCF Master => read more
  • 2018-05-23 NetTimeLogic proudly announces that it is now a Xilinx Alliance Program Member => read more
  • 2018-04-25 NetTimeLogic joined the HardwareBee network => read more
  • 2018-02-14 NetTimeLogic will attend Embedded World 2018 in Nuernberg Germany: February 28th - March 1st
  • 2017-12-28 NetTimeLogic announce DCF Products, in particular a DCF Slave which can synchronize to the DCF77 sender near Frankfurt, Germany with an accuracy better than one millisecond => read more
  • 2017-11-14 NetTimeLogic developed and provides a PPS Analyzer device for the swiss PTP Plugfest =>  read more
  • 2017-10-03 NetTimeLogic is proud organizer and sponsor of the first swiss PTP Plugfest in Winterthur => read more
  • 2017-09-12 Successful testing of our cores at ISPCS2017, NetTimeLogic introduced the "ISPCS proved" logo for all the cores tested sucessfuly at ISPCS => read more
  • 2017-08-18 PTP Tap beta version released => read more
  • 2017-07-19 HSR/PRP Manual released => read more
  • 2017-06-16 HSR/PRP released => read more
  • 2017-04-01 NetTimeLogic is proud Silver sponsor of ISPCS2017 in Monterey => read more
  • 2017-03-18 NMEA Master released => read more
  • 2017-03-14 NetTimeLogic at Embedded World in Nurnberg
  • 2017-02-10 Pricing of allour products updated
  • 2017-01-06 RTC Master Clock released => read more
  • 2016-12-28 Free Configuration Tool beta release => read more
  • 2016-12-08 NetTimeLogic announces Real Time Clock (RTC) Master core allowing to read and write RTC clocks via I2C without time format conversion. Clock accuracy in the range of +/- 100 ns is achieved. This allows storing and recovering time from a non volatile storage => read more2016-11-09 IRIG-B Master and Slave released => read more
  • 2016-10-28 IRIG-B up and running andsynchronizing accurate to +/-20 ns2016-10-27 NetTimeLogic moved the Headquarter to it's new office
  • 2016-09-04 NetTimeLogic is testing and presenting at the ISPCS2016
  • 2016-08-25 First redundant PTP node ready for beta testing
  • 2016-08-24 NetTimeLogic is partnering with Enclustra GmbH, not only will we share our expertise but also we will use Enclustra's Mars series AX3/PM3 hardware for additional reference designs => read more
  • 2016-08-12 NetFPGA CML was added as a new reference hardware for NetTimeLogics IP cores
  • 2016-08-09 Added Reference Manuals to website for some of the cores
  • 2016-05-06 NetTimeLogic is proud sponsor of ISPCS2016 in Stockholm => read more
  • 2015-04-27 Added network redudndancy cores to NetTimeLogics products => read more
  • 2016-02-28 Website update for multiple cores, adapted pricing, discounts and licensing
  • 2016-01-29 Reference designs for PTP OC/TC/HC/GM and PPS Master/Slave created for Altera's SoCkit and Xilinx Arty development boards, free demo donwloads will follow soon >> read more
  • 2016-01-10 PPS Master and Slave implemented and tested >> read more
  • 2015-10-14 NetTimeLogic succesfully tested OC/TC/HC at ISPCS2015 in Beijing >> read more
  • 2015-10-11 NetTimeLogic attended ISPCS2015 in Beijing
  • 2015-09-11 Flyers of PTP OC, TC and HC added.
  • 2015-09-10 NetTimeLogic will take part in the Industrial Day of the ISPCS >> read more
  • 2015-07-09 NetTimeLogic will take part in the ISPCS Plufest in Beijing to verify PTP cores. >> read more
  • 2015-06-11 NetTimeLogic is part of "Swiss Made Software". >> read more

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