NetTimeLogic developed a PPS analyzer specifically for (PTP) Plugfests where multiple devices are synchronizing each other, and the accuracy of the individual devices shall be measured via PPS (offset from reference PPS). The device has 8 PPS inputs that are measured simultaneously, and it synchronizes itself to an additional reference PPS input. Additionally, it has a PPS output of the synchronized clock which is used for PPS measurement. Multiple PPS Analyzers can be connected to the same host and are all discovered automatically. It uses a serial interface (mostly over USB) or Ethernet to access the registers in the FPGA. In the FPGA it uses NetTimeLogic's configuration IP (free of charge) which represents an AXI Master to the other IP cores. It uses a proprietary protocol to convert the serial data stream from/to AXI register access. The core part consists of the following NetTimeLogic IP cores: PPS Slave IP core, PPS Master IP core, Adjustable Counter Clock IP core and multiple instances of the Signal Timestamper IP core. The tool needs no configuration and self-discovers all cores available in the design. It allows to access all registers in the design (also third party) which are connected to the AXI bus.
It allows to save the measurement screen as JPG, PNG or TIFF and can log the measured values as CSV.
The application is written with Qt as GUI framework and is currently available for Windows. The measured offsets are read by the PPS Analyzer application via UART and shown in a chart.
