PPS Analyzer

PPF proved

NetTimeLogic developed a PPS analyzer specifically for (PTP) Plugfests where multiple devices are synchronizing each other, and the accuracy of the individual devices shall be measured via PPS (offset from reference PPS). The device has 8 PPS inputs that are measured simultaneously, and it synchronizes itself to an additional reference PPS input. Additionally, it has a PPS output of the synchronized clock which is used for PPS measurement. Multiple PPS Analyzers can be connected to the same host and are all discovered automatically. It uses a serial interface (mostly over USB) to access the registers in the FPGA. In the FPGA it uses NetTimeLogic's configuration IP (free of charge) which represents an AXI Master to the other IP cores. It uses a proprietary protocol to convert the serial data stream from/to AXI register access. The core part consists of the following NetTimeLogic IP cores: PPS Slave IP core, PPS Master IP core, Adjustable Counter Clock IP core and multiple instances of the Signal Timestamper IP core. The tool needs no configuration and self-discovers all cores available in the design. It allows to access all registers in the design (also third party) which are connected to the AXI bus.

It allows to save the measurement screen as JPG, PNG or TIFF and can log the measured values as CSV.

The application is written with Qt as GUI framework and is currently available for Windows. The measured offsets are read by the PPS Analyzer application via UART and shown in a chart.

Block Diagram

PPS Analyzer


The hardware used for the PPS Analyzer consists of a custom PPS shield for the ArtyA7-35T board from Digilent

PPS Shield

PPS Analyzer shield from Christian Voit (available for freeas EAGLE(R) Schema and Layout with BOM for DIY)

PPS Analyzer

Prototype implementation of the PPS Analyzer shield


PPS Screen

Grey: Reference PPS, Purple: PPS from device under test (4000+ seconds run)

This is the screen to change the individual delays in case cable delays differ or the input buffers have slightly different delays

This is a saved screen (you can save the current screens as PNG, TIFF or BMP) from the swiss PTP Plugfest 2017


  • 8 PPS inputs per analyzer
  • 1 reference PPS input per analyzer
  • 1 PPS output per analyzer
  • Synchronized Clock via PPS
  • Timestamp resolution 4ns
  • PPS compensated for synchronization error introduced by the reference PPS
  • Multiple Analyzers supported (in the same Screen)
  • Individual Delay compensation per PPS
  • Enable and disable individual PPS
  • Auto scale or fixed scale
  • Longterm measurements (up to 100000 seconds) with sliding screen window)
  • Self-discovery of all Analyzers
  • Save screen as PNG, TIFF or BMP
  • Log values as CSV

Lend or build your own

The PPS analyzer is not for sale but it can be lent for a limited time => contact us

If you want to build your own, we are happy to give you the required information how to build your own PPS shield and we will provide the GUI software, a bitstream, and EAGLE(R) schematics, layout and BOM files (HW files provided by Christian Voit) for the ArtyA7-35T board => contact us to get free access to the download page

The GUI is available on Github: https://github.com/NetTimeLogic/UniversalPpsAnalyzer


Upa_UniversalPpsAnalyzer_ReferenceManual.pdf Upa_UniversalPpsAnalyzer_ReferenceManual.pdf
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