NetTimeLogic offers full time synchronization, network redundancy, an time sensitive networking solutions as vendor independent FPGA IP cores. Full hardware implementations of synchronization IP cores such as PTP-Transparent-, Ordinary-, Grandmaster- or Hybrid-Clocks as well as IRIG-, PPS-, NMEA-Masters and Slaves and a RTC-Master and a DCF-Slave. For network redundancy we provide a full hardware implementation of the HSR and PRP protocols and for time sensitive networking we provide also a full hardware implementation of TSN. All IP cores can be combined to a complete synchronization or network redundancy solution which can act e.g. as bridge between the different times synchronization protocols or as a network redundancy solution with time synchronization support.