Whitepapers

Here you can find some Whitepapers from NetTimeLogic. Some of them were previously published on Tumblr or LinkedIn, so follow us on LinkedIn

Resiliency with Majority Voting and Source Selection

15 July 2025

NetTimeLogic’s AIONYX platform ensures sub-µs accurate timing under GNSS attacks using multiple receivers, a high-stability oscillator, majority voting, and advanced holdover with alternative references.

Performant Rust Webserver on a Low-Cost FPGA

4 April 2025

NetTimeLogic runs a Rust-based web server on a Hive-S FPGA (Artix™ 7) with a 125 MHz RISC-V soft CPU, delivering memory-safe, responsive web interfaces without a dedicated CPU.

Lucky-Packet and Outlier Filters for Improved PTP Synchronization

2 April 2025

NetTimeLogic IP Cores use Lucky-Packet selection and Outlier Filters to improve PTP timing from ±20 µs to ±200 ns while increasing resilience against erroneous measurements.

1 Nanosecond Signal Generation Accuracy on an FPGA

17 April 2024

NetTimeLogic generates 1 ns-accurate FPGA signals using a DTC with tapped delay lines and coarse/fine clocks, enabling precise PPS output in Signal Generator, Frequency Generator, and PPS Master IP cores.

1 Nanosecond Timestamp Accuracy on an FPGA

5 April 2024

NetTimeLogic achieved 1 ns timestamp resolution on low-cost FPGAs using a TDC with tapped delay lines, coarse/fine clocks, and compensation, enabling high-precision timestamps for Signal Timestamper, PPS Slave, and PPS Analyzer.

1 Nanosecond Timestamp Accuracy on an FPGA.pdf 1 Nanosecond Timestamp Accuracy on an FPGA.pdf
Size : 452.144 Kb
Type : pdf

AIONYX – Some Insights

4 April 2024

NetTimeLogic’s AIONYX is a modular FPGA platform with swappable Pmod™/Zmod™ modules for GNSS, PLLs, Ethernet, and IO, supporting industrial-grade, high-precision time-synced applications like PTP Grandmasters, TSN nodes, and Edge Servers.

AIONYX - Some insights.pdf AIONYX - Some insights.pdf
Size : 4681.601 Kb
Type : pdf

Full Hardware FlashPTP Client-Server

8 March 2024

NetTimeLogic’s FPGA-based FlashPTP Client and Server deliver sub-20 ns PPS accuracy with minimal message overhead, stateless operation, and full IEEE1588 compatibility. Scalable, low-latency, and interoperable, it provides a future-proof foundation for CSPTP

IRIG-G extension to IRIG corE

17 February 2022

NetTimeLogic extended its IRIG core with IRIG-G support, transmitting 100 frames per second with millisecond resolution. DCLS processes every 100th frame to reduce jitter. For AM-modulated IRIG-G, low-cost 1 MSPS DACs/ADCs work by shaping the sine wave into a pseudo-square wave, improving zero-crossing detection and surpassing IRIG-B accuracy. Higher sampling rates (2–5 MSPS) increase reliability.

IRIG-G extension to IRIG core.pdf IRIG-G extension to IRIG core.pdf
Size : 477.055 Kb
Type : pdf

High-Performance NTP Server

28 September 2021

NetTimeLogic’s FPGA-based (S)NTP Server handles 100k+ requests/s with minimal resources—no CPU or software stack needed—delivering high efficiency and best-in-class requests/watt.

High performance NTP Server.pdf High performance NTP Server.pdf
Size : 710.636 Kb
Type : pdf

FreeRTOS/lwIP on a NIOS II Softcore to run open62541

28. April 2020

NetTimeLogic demonstrates that open62541 can also run on an Intel (Altera) NIOS II Soft-Core using FreeRTOS and lwIP. A reference design on the Trenz Cyclone 10 LP RefKit enables Ethernet communication via SGDMA and TSE MAC, while the updated BSP and CMake setup allow a PubSub example to run from SDRAM at 100 MHz, showing promising soft-core performance compared to MicroBlaze.

Open62541 publishing performance on a Soft-Core CPU in an FPGA

11 February 2020

NetTimeLogic shows that MicroBlaze Soft-Cores can efficiently run open62541 PubSub. FIXED_SIZE RT mode maximizes frame rate, though dynamic updates are limited. Deterministic behaviour and TSN integration are next.

OPC UA PubSub on a FPGA using open62541

2 October 2019

NetTimeLogic shows that open62541 PubSub can run on a MicroBlaze Soft-Core in an FPGA. The example demonstrates dataset publishing with FreeRTOS/lwIP, customizable nodesets, and TSN-ready integration. Some header adaptations were required for full compatibility with the IIC TSN Testbed.

OPC UA PubSub on a FPGA using open62541.pdf OPC UA PubSub on a FPGA using open62541.pdf
Size : 1135.542 Kb
Type : pdf

OPC UA server on a FPGA using open62541

30 August 2019

NetTimeLogic demonstrates how open62541 can run on a MicroBlaze Soft-Core in an FPGA. The example shows server setup under FreeRTOS with lwIP, including BSP adjustments, CMake configuration, and buffer tuning for reliable network communication. Connected LEDs on the Arty A7 board can be controlled via OPC UA, providing a full industrial communication 4.0 demo.

OPC UA server on a FPGA using open62541.pdf OPC UA server on a FPGA using open62541.pdf
Size : 2910.978 Kb
Type : pdf

IRIG-B12x with DAC and ADC

27 August 2018

NetTimeLogic enables <1 µs IRIG-B12x sync using low-cost DACs/ADCs at 1 MSPS. FPGA handles sine wave encoding/decoding, SPI transfers at 500 kHz, and delays are compensated. Fine-tuned PI servo improves accuracy to ±800 ns.

IRIG-B12x with DAC and ADC.pdf IRIG-B12x with DAC and ADC.pdf
Size : 1178.77 Kb
Type : pdf

Presentations

Here you can find some Presentations from NetTimeLogic previously presented at conferences NetTimeLogic attended.

Timing Related Capabilities CPUs vs MCUs vs FPGAs

7 November 2024

NetTimeLogic gives a comprehensive overview of the different timing capabilities of CPUs, MCUs and FPGAs. What are the strengths, limitations and typical use-cases of the different solutions. How do they compare when it comes to real-time applications, timestamping, time-triggered events, frequency generation and phase/frequency adjustments.

Time Card with PCIe PTM support - Capabilities and benefits

10 October 2024

NetTimeLogic added PCIe PTM support to the OCP TAP Time Card which NetTimeLogic did the whole FPGA Designand shows the capabilities and benefits of using PTM.

NTP and Client-Server PTP fully in Hardware -1 Mio Requests with less than 3 Watts

10 October 2024

NetTimeLogic implemented an NTP Server and Client-Server PTP (CSPTP) Server fully in hardware to demonstrate how a low cost and low power FPGA can outperform any highend CPU based Server (1Mio Requests per Second) while still using less than 3 Watts.

Network Timing and Network Redundancy, the Many Approaches to Resilient Time Distribution

1 November2023

NetTimeLogic shows the different Network Redundancy protocols and how they are combined with Network Timing protocols like PTP and NTP and demonstrate what is possible with the different Network Redundancy protocols when it comes to fault tolerance, down- and recovery-times and accuracy.

Time Card and Open Time Server

6 October 2022

The Time Card is an open-source PCIe card that provides time accuracy
for the Open Time Servers. NetTimeLogic, as the developers of the core FPGA, explores some of the capabilities and advantages of the Time Card and the Open Time Server.

Time Card and Open Time Server.pdf Time Card and Open Time Server.pdf
Size : 2628.437 Kb
Type : pdf

TSN - what is it and how can it be implemented using FPGA technology

3 September 2019

NetTimeLogic implements different Time Sensitive Networking (TSN) solutions on FPGAs and explains what TSN is and how it can be implemented using FPGA Technology.

Wireless IEEE1588 over an Infrared Interface

8 September 2016

NetTimeLogic invented a solution to use IEEE1588 over a wireless link, in particular over an infrared interface. One part of the invention includes the embedding and timestampingof Ethernet Frames into a UART like interface used on the infrared link.