Ioannis Sotiropoulos
FPGA Design Engineer
Ioannis Sotiropoulos has a master's degree in computer science from the EPFL École Polytechnique Fédérale de Lausanne (Switzerland) and a diploma in electronics and computer engineering of theTechnical University of Crete, Greece.
Ioannis is a principal FPGA Design Engineer at NetTimeLogic.
He has in-depth knowledge in time synchronization, ethernet, data processing, FPGA. Over the last years he developed several FPGA IP cores for the utilities industry.
Ioannis Sotiropoulos is involved in multiple standardization activities in the area of time synchronization and nework redundancy and created several papers in these areas:
- Performance of a full-hardware PTP implementation for an IEC 62439-3 redundant IEC 61850 substation automation network
- Precise time synchronization in Digital Substations (CIGRE 2018)
- Determinism in Substation Automation with IEC61850 (PACW 2017)
Ioannis Sotiropoulos is co-author of 3 patents:
- Device and method for providing a clock signal to an application
- Redundant content bridging between substation automation networks
- Boundary clock over multiple Ordinary clocks (defensive publication)