NetTimeLogic provides two different IRIG cores, an IRIG Master and an IRIG Slave. Both support DCLS and AC encoding (for AC encoding external DACs and ADCs are used)
All cores are in plain VHDL and completely FPGA vendor independent. The protocols are implemented as full hardware cores, no soft-core CPUs are used.
The IRIG Master from NetTimeLogic is a full hardware only implementation of an IRIG Master to distribute time via IRIG.
The IRIG Slave from NetTimeLogic is a full hardware only implementation of an IRIG parser and synchronizer. It allows to synchronize the local clock to IRIG without the need of software or a soft-core CPU.