Adjustable Clock

The Adjustable Clock from NetTimeLogic is an adjustable counter clock with nanosecond resolution (second and nanosecond format). It is used by all other cores from NetTimeLogic but can also be used as standalone core. It contains a hardware implemented PI servo loop (which also can be bypassed) for smooth adjustment of drift and offset. Drift and Offset correction are adjusted in parallel and individual. It can take any input frequency, even with non-integer clock periods (e.g. 66MHz) which is handled with fractional subcounters. It has multiple adjustment inputs which are multiplexed to define the source of synchronization.

An optional add-on core allows to also adjust the frequency directly on a SiTime oscillator via I2C.

All calculations and corrections are implemented completely in HW.
The IP core comes with a Linux Driver

Block Diagram

Adjustable Clock


  • 32 bit second and 32 bit nanosecond counter clock with fractional extention
  • 1  millisecond pulse generator aligned with the counter clock
  • Allows non-integer clock periods
  • Multiplexing of multiple adjustment inputs
  • AXI4 Light register set or static configuration
  • Evenly spread offset and drift correction (offset might be set hard in case of large offsets)
  • Hard setting of time possible
  • Individual hardware only PI servo loops for offset and drift correction (PI parameters individually configurable)
  • Runtime changeable PI servo parameters
  • Offset correction: min 1/2^16 ns / s, max 0.5 s/s
  • Drift correction: min 1/2^16 ns / s, max 0.05 s/s
  • Conversion of fractional adjustments into even spread clock adjustments
  • Optional add-on core to also adjust the drift directly on a SiTime oscillator via I2C.
  • Provides time for all other cores
  • Logging of correction values
  • Linux Driver (PHC)

Licensing & Pricing

There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  4100$
  • Site Source Code: 7400$ 

All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.


Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries  => contact us for free access

Clk_Clock_Flyer.pdf Clk_Clock_Flyer.pdf
Size : 114.968 Kb
Type : pdf
Clk_Clock_ReferenceManual.pdf Clk_Clock_ReferenceManual.pdf
Size : 1112.298 Kb
Type : pdf