Time Sensitive Networking (TSN) Products
NetTimeLogic provides complete FPGA based Time Sensitive Networking (TSN) solutions based on its redundancy and time synchronization solutions. The TSN solutions supports all major TSN protocols which are in charge of e.g. time synchronization, network redundancy, priority handling, deterministic forwarding, time slotting / traffic scheduling, preemption and different traffic shaping.
All cores are in plain VHDL and completely FPGA vendor independent. The protocols are implemented as full hardware cores, no soft-core CPUs are used.
TSN Network Node
The TSN Network NodeIP core from NetTimeLogic is a 3 port (2 redundant ports and 1 uplink) network node built from NetTimeLogic's Redundancy and PTP Hybrid Clock cores, which were extended with TSN features like scheduling, priority queues, credit shaping, cyclic forwarding and preemption. It also supports seperate AXI stream interfaces directly to and from the priority queues to handle data from within the FPGA.
TSN End Node
The TSN End Node IP core from NetTimeLogic is a TSN aware single port End Node. It supports the same features as the TSN Network Node core except network redundancy.It is meant as a TSN co-processor enabling non-TSN aware interfaces to support TSN features like scheduling, priority queues, credit shaping, cyclic forwarding and preemption. It also supports seperate AXI stream interfaces directly to and from the priority queues to handle data from within the FPGA.
TSN IIC(R) Plugfest Application
NetTimeLogic offers a companion core for its TSN IP cores to have an easy solution to take part in the IIC(R) TSN Testbed/Plugfests. It implements an OPC/UA Talker and Listener, the Analysis and Statistics Application as well as the Statistics Publisher and LED Application (Source and Sink).
Size : 436.567 Kb
Type : pdf