NetTimeLogic provides two TOD (Time of Day) cores a TOD Master and a TOD Slave. All cores are in plain VHDL and completely FPGA vendor independent. The protocols are implemented as full hardware cores, no soft-core CPUs are used.
TOD Master
The TOD Master from NetTimeLogic is a full hardware only implementation of an NMEA creator and distributor. It allows to synchronize other nodes via NMEA messages without the need of software or a soft-core CPU.
The TOD Slave from NetTimeLogic is a full hardware only implementation of an NMEA, UBX and TSIP message parser and synchronizer. It allows to synchronize the local clock to NMEA, UBX, TSIP and ESIP messages without the need of software or a soft-core CPU.
