Thomas Schaub holds a bachelor degree in Electrical Engineering from the University of Applied Sciences FHNW (Switzerland).
Thomas Schaub is Business Partner and Principal FPGA & Hardware Design Engineer at NetTimeLogic.
He has extensive knowledge in time synchronization, Ethernet, data processing, FPGA, software and hardware development, as well as testing and project management (SCRUM Master). During the last 15 years he has developed several FPGA IP cores and hardware modules. Thomas is the maintainer of the Time Card FPGA designs.
Thomas Schaub is part of the TSN/A conference committee and has written several papers/publications/articles/webinars in the area of TSN and Time Synchronization:
