IRIG Slave

NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004, B005, B006 and B007 Master. The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

Block Diagram

 

Synchronization Accuracy

100ns per division on oscilloscope

The synchronization accuracy achieved with a 50MHz oscillator is around +/-25ns

Features

  • IRIG Slave Clock
  • Supports IRIG-B006 format (compatible with B004, B005, B006 and B007 IRIG-B Masters)
  • Optional support Control Bits for IRIG-B000/B001/B004/B005
  • Optional AC decoding and amplitude demodulation for IRIG-B120 - B127 (requires an external ADC)
  • IRIG decoding and time format conversion
  • IRIG supervision
  • Input delay compensation
  • Cable delay compensation
  • Additional seconds correction to convert between UTC and TAI time (or any other time base)
  • Synchronization accuracy: +/- 25ns
  • AXI4 Light register set or static configuration
  • Timestamp resolution with 50 MHz system clock: 20ns
  • Hardware PI Servo

Licensing & Pricing

There are different licensing possibilities. All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  2700$
  • Site Source Code: 4900$

Downloads

Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access

Irig_Slave_Flyer.pdf Irig_Slave_Flyer.pdf
Size : 118.637 Kb
Type : pdf
Irig_Slave_ReferenceManual.pdf Irig_Slave_ReferenceManual.pdf
Size : 695.621 Kb
Type : pdf