NetTimeLogic GmbH - IRIG Master

IRIG Master

NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via IRIG-B007/IRIG-G006. The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

Block Diagram

Features

• IRIG-B Master Clock
• Supports IRIG-B007 and IRIG-G006 format (compatible with B004, B005, B006 and B007 IRIG-B Slaves)
• Optional supports all IRIG-B000 - B007 codes, changeable at runtime
• Optional supports Control Bits for IRIG-B000/B001/B004/B005
• PWM, DCLS encoding
• Optional AC encoding and amplitude modulation for IRIG-B120 - B127 and IRIG-G146(requires an external DAC)
• Output delay compensation
• Additional seconds correction to convert between TAI and UTC time (or any other time base)
• AXI4 Light register set or static configuration
• IRIG resolution with 50 MHz system clock: 20ns (DCLS)

Licensing & Pricing

There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

• Project Source Code:  3100$
• Site Source Code: 5600$

All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.

Downloads

Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access