Kevin Schärer has a master degree in electrical engineering from the ETH Swiss Federal Institute of Technology Zurich (Switzerland).
Kevin is a Hardware, Software and FPGA Design Engineer at NetTimeLogic.
He has in-depth knowledge in FPGA, software and hardware development. At NetTimeLogic he developed several hardware designs (PWR, ADC, DAC, etc.)for our AIONYX platform, an FPGA IP core for frequency adjusting oscillators and is the developer of NetTimeLogic's Universal Web Manager (UWM) running on the AIONYX platform.
