NetTimeLogic GmbH - PTP Ordinary Clock

The PTP Ordinary Clock (OC) from NetTimeLogic is an extension to a single port of NetTimeLogic's PTP Transparent Clock (TC). It adds the Sync and Announce message processors to the design which allow synchronization of the clock according to IEEE1588.  The OC will run in Slave or Master mode according to the configuration and Best-Master-Clock (BMC) algorithm. For resource optimization the OC can also be implemented as Slave-Only clock.

The OC is intercepting the path between an Ethernet PHY and an Ethernet MAC. This allows message injection in parallel to data transfers from/to the MAC.

All datasets and algorithms are implemented completely in HW.

Block Diagram

Synchronization Accuracy

100ns per division on oscilloscope

The synchronization accuracy achieved with a 50MHz oscillator is around +/-25ns

Features

• PTP Ordinary Clock according to IEEE1588-2019/2008
• Intercepts path between MAC and PHY
• Single Port
• Synchronization accuracy: +/- 25ns
• Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (Ip) support
• Support for Power Profile: C37.238-2011 and C37.238-2017 including VLAN support
• Support for Utility Profile: including HSR and PRP tag handling
• Support for IEEE802.1AS-REV: including IEEE802.1CB tag handling
• One Step and Two Step support
• Peer to Peer (P2P) and End to End (E2E) delay measurement
• Master and Slave support
• Full line speed
• AXI4 Light register set or static configuration
• Datasets according to IEEE1588
• MII/RMII/GMII/RGMII Interface support (optional AXI4 stream for interconnection to 3rd party cores)
• Optional Management Message support
• Optional Signaling Message support
• Optional 10G XGMII extension (requires add-on license)
• Timestamp resolution with 50 MHz system clock: 10ns, with high resolution clock 4ns
• Hardware PI Servo

Licensing & Pricing

There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

• Project Source Code: 7700$
• Site Source Code: 13900$

All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.

Downloads

Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access