PTP Hybrid Clock

ISPCS proved

The PTP Ordinary Clock (OC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock (OC). It adds the Sync and Announce message processors to the design which allow synchronization of the clock according to IEEE1588 while keeping the timing aware frame forwarding feature of the TC.  The OC will run in Slave or Master mode according to the configuration and Best-Master-Clock (BMC) algorithm. For resource optimization the OC can also be implemented as Slave-Only clock.

The HC is intercepting the path between an Ethernet PHY and an Ethernet core that forwards or handles Ethernet frames. Mostly this is used in daisy-chained networks. This allows message injection in parallel to data transfers from/to the Switching Core.

All datasets and algorithms are implemented completely in HW.

Block Diagram

Features

  • Combined PTP Ordinary Clock and PTP Transparent Clock according to IEEE1588-2008
  • Intercepts path between MAC and PHY
  • Two (TC) plus one (OC) Port, used for daisy chaining or redundancy protocols
  • Synchronization accuracy: +/- 25ns
  • Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (Ip) support
  • Support for Power Profile: C37.238-2011 and C37.238-2017 including VLAN support
  • Support for Utility Profile: including HSR and PRP tag handling
  • Support for IEEE802.1AS-REV: including IEEE802.1CB tag handling
  • One Step and Two Step support
  • Peer to Peer (P2P) and End to End (E2E) delay measurement
  • Master and Slave support
  • Full line speed
  • AXI4 Light register set or static configuration
  • Datasets according to IEEE1588
  • MII/GMII/RGMII Interface support (optional AXI4 stream for interconnection to 3rd party cores)
  • Optional Management Message support
  • Optional Signaling Message support
  • Timestamp resolution with 50 MHz system clock: 10ns
  • Hardware PI Servo

Licensing & Pricing

There are different licensing possabilities. All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  8100$
  • Site Source Code: 14600$


All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.

Downloads

Evaluation binaries available for Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access

Ptp_HybridClock_Flyer.pdf Ptp_HybridClock_Flyer.pdf
Size : 348.967 Kb
Type : pdf
Ptp_HybridClock_ReferenceManual.pdf Ptp_HybridClock_ReferenceManual.pdf
Size : 3256.572 Kb
Type : pdf