NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes to a Pulse per Second output. The whole algorithms and calculations are implemented in the core, no CPU is required. This allows running PPS synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
- PPS Master Clock
- Output delay compensation
- PPS duty cycle adjustment, width can be set via register
- AXI4 Light register set or static configuration
- PPS resolution with 50 MHz system clock: 10ns
Licensing & Pricing
There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:
- Project Source Code: 2000$
- Site Source Code: 3600$
All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.
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