
![]() |
Pps_Slave_Flyer.pdf Size : 134.047 Kb Type : pdf |
![]() |
Pps_Slave_ReferenceManual.pdf Size : 729.06 Kb Type : pdf |
NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Pulse per Second input. The whole algorithms and calculations are implemented in the core, no CPU is required. This allows running PPS synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
There are different licensing possibilities (more info here). All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:
All prices are non-binding estimates – please use the contact form for definitive pricing and lead-time information.
Evaluation binaries available for Digilent's Arty and Terasic's SoCKit development boards or as Modelsim(R) precompiled libraries => contact us for free access
![]() |
Pps_Slave_Flyer.pdf Size : 134.047 Kb Type : pdf |
![]() |
Pps_Slave_ReferenceManual.pdf Size : 729.06 Kb Type : pdf |