The Universal Time Sync (UTS) is an all-in-one time synchronization solution which allows you to create your synchronization system with minimal effort and costs. It is the swiss-army-knife of synchronization. The UTS core consists of several subcores which can be tailored as needed. In the full version, all cores are interconnected as shown below.
Each time synchronization core (NMEA, PPS, IRIG, PTP) can be instantiated individually. Also, the number of timestamper- and signal- or frequency-generator cores can be chosen according to your needs.
Each core has its own AXI4 Lite Slave register interface to allow some additional configuration or read out the status of each individual core. All cores can be also statically configured without the need for a CPU.
The interfaces of the cores are kept as lean as possible and only standard interfaces (AXI4, MII/GMII, UART, IRIG ...) are used to the user logic to also give the possibility to interconnect to third-party cores.
