FPGA Services

As with CPUs also FPGAs get bigger and bigger and more and more complex. With our experience and know how we are able to cope with even the most complex designs. We set the focus in our development on modularity, reausability, simulation and testability which in the end often leads to simplicity even if the design is very large and in itself complex. This allows us to use the same development flow for simple and very complex designs.

We use source control, ticketing and automated build systems to keep track of the development and simplify the development flow.

We can help you in every step of FPGA development: from simple entities to complete IP core solutions:

  • Design, Concept and Architecture of your system
  • Resource and power estimations
  • Implementation of entities
  • Modul level testbenches
  • Testbench frameworks
  • Transaction based top level testbenches with stimuli files
  • Stimuli files for testbenches
  • Simulation scripting for Modelsim
  • Project scripting for Xilinx and Altera
  • Timing constraints
  • Pinout constraints
  • Placement constraints for very high frequency designs
  • Timing closure
  • Synthesis
  • Place and Route optimization
  • Hardware test platforms
  • Stimuli files for hardware test platforms
  • Debugging on hardware
  • Regression testing
  • Deployment and continuous integration
  • Maintenance
  • Education
  • And much more ...

We use FPGAs of the following vendors:

* logo copyrights at FPGA vendors

FPGA Design Expertise

We have experience in a wide area of FPGA based designs, this is just a short summary of the most recent designs we worked on:

  • PPS analyzing device
  • Data aquisition unit
  • Ethernet Network Tap with VSS Monitoring Trailer
  • Synchronization of distributed systems via PTP (IEEE1588), IRIG-B, NMEA, PPS and GPS
  • High availability networks with PRP and HSR support (IEC62439)
  • Ethernet Network Switch
  • Ethernet based communication, MAC in an FPGA
  • Realtime Ethernet core in an FPGA
  • PC to FPGA communication for register access and data aquisition
  • Servo loops in FPGA
  • Infrared communication link
  • LED matrix controller
  • VGA Display controller
  • Flash and RAM controller
  • SPI and I2C controller
  • Data aquisition unit and data pre processing
  • Softcore (NIOS II and Microblaze) integration and SoC (Xilinx Zynq and Altera SoC) development
  • AXI Slave and Master implementations
  • Transaction based testbenches and hardware test platforms
  • Design porting between different FPGA vendors and FPGA families
  • FPGA Workshops at Dock18 (code & presentation, video)
  • And much more ...

For our designs we developed a library with the most common building blocks (RAM, FIFOs, AXI, CRC calculation, etc.) and a simulation frameworkand library (PPS, PTP, IRIG, UART, AXI, etc.) that can be reused and extended for new projects to save time for the development.


  • Design entry:
    • VHDL (preferred)
    • Verilog
  • Verification:
    • VHDL
    • TCL
    • ASCII Text
  • Synthesis, place and route, static timing analysis:
    • TCL
    • QSF
    • SDC
    • XDC
    • UCF

Development Tools

  • Design Concept:
    • Microsoft Visio
    • Microsoft Word
  • Design entry:
    • Notepad ++
    • Eclipse
    • Altera QSYS
    • Xilinx IPI
  • Verification:
    • Mentor Graphics Modelsim
  • Synthesis, place and route, static timing analysis:
    • Altera/Intel Quartus II
    • Xilinx Vivado
  • Debugging
    • Altera/Intel SignalTap II
    • Xilinx ChipScope
  • Continuous Integration
    • GIT
    • Jenkins


Contact us for our rates, rates depend on the duration and tasks to be done

contact us