Universal Configuration Manager
NetTimeLogic's Universal Configuration Manager is a complete configuration solution that allows to configure, manage and supervise all IP cores from NetTimeLogic in an FPGA. It uses a serial interface (mostly over USB) to access the registers in the FPGA. In the FPGA it uses NetTimeLogic's configuration IP (free of charge) which represents an AXI Master to the other IP cores. It uses a proprietary protocol to convert the serial data stream from/to AXI register access. The tool needs no configuration and self-discovers all cores available in the design. It allows to access all registers in the design (also third party) which are connected to the AXI bus.
The apllication is written with Qt as GUI framework and currently available for Windows
=> in beta phase
This is an example of a design with three cores. (This is only an example and can be changedto any other configuration.)
- Preconfigured GUI Tabs for NetTimeLogic's IP cores
- Status charts for certain values (e.g. delay and offset)
- Read and Write all Registers of all IP cores
- Read and Write any AXI address
- Selfdiscovery of instanciated IP cores
Licensing & Pricing
Free of charge, licensed under LGPL
PTP Ordinary Clock Ip core screen, allowing to access the PTP data sets and monitoring the calculated offset and delay in real time (here constant zero because of internal measurement)
PTP Transparent Clock Ip core screen, allowing to access the PTP data sets and monitoring the delay in real time of all poprts (third port here constant zero because of internal measurement)
Configuration screen showing the address map of the available cores.
Advanced screen allowing to read and write to any AXI address.
Clock IP core screen, allowing to read/write the time and check the status.
Redundancy IP core screen, allowing to read/write the MAC and redundancy mode and check the status.
The whole project can be found as sources on NetTimeLogic's Github account:
Contact us if you would like to contribute to the development of this open source project
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