IRIG Master

NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via IRIG-B007/B127 . The whole encoding, convertion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

Block Diagram

Features

  • IRIG-B Master Clock
  • Supports IRIG-B007/B127 format (compatible with B004/B124, B005/B125, B006/B126 and B007/B127 IRIG-B Slaves)
  • PWM, DCLS encoding
  • Output delay compensation
  • Additional seconds correction to convert between TAI and UTC time (or any other time base)
  • AXI4 Light register set or static configuration
  • IRIG resolution with 50 MHz system clock: 20ns

Licensing & Pricing

There are different licensing possabilities. All prices are in US Dollars without VAT, all prices are one-time fees, no royalities apply:

  • Project Source Code:  2700$
  • Site Source Code: 4900$

Downloads

Evaluation binaries available for Digilent's Arty and Terasic's SoCKit develolopment boards => contact us for free access

Irig_Master_Flyer.pdf Irig_Master_Flyer.pdf
Size : 258.61 Kb
Type : pdf
Irig_Master_ReferenceManual.pdf Irig_Master_ReferenceManual.pdf
Size : 952.788 Kb
Type : pdf