NEWS

Here you can find the latest news about NetTimeLogic's activities.

You can find news also on our social media pages:

News

  • 2017-06-16 HSR/PRP released => read more
  • 2017-04-01 NetTimeLogic is proud Silver sponsor of ISPCS2017
  • 2017-03-18 NMEA Master released => read more
  • 2017-03-14 NetTimeLogic at Embedded World in Nurnberg
  • 2017-02-10 Pricing of allour products updated
  • 2017-01-06 RTC Master Clock released => read more
  • 2016-12-28 Free Configuration Tool beta release => read more
  • 2016-12-08 NetTimeLogic announces Real Time Clock (RTC) Master core allowing to read and write RTC clocks via I2C without time format conversion. Clock accuracy in the range of +/- 100 ns is achieved. This allows storing and recovering time from a non volatile storage => read more2016-11-09 IRIG-B Master and Slave released => read more
  • 2016-10-28 IRIG-B up and running andsynchronizing accurate to +/-20 ns2016-10-27 NetTimeLogic moved the Headquarter to it's new office
  • 2016-09-04 NetTimeLogic is testing and presenting at the ISPCS2016
  • 2016-08-25 First redundant PTP node ready for beta testing
  • 2016-08-24 NetTimeLogic is partnering with Enclustra GmbH, not only will we share our expertise but also we will use Enclustra's Mars series AX3/PM3 hardware for additional reference designs => read more
  • 2016-08-12 NetFPGA CML was added as a new reference hardware for NetTimeLogics IP cores
  • 2016-08-09 Added Reference Manuals to website for some of the cores
  • 2016-05-06 NetTimeLogic is proud sponsor of ISPCS2016 in Stockholm => read more
  • 2015-04-27 Added network redudndancy cores to NetTimeLogics products => read more
  • 2016-02-28 Website update for multiple cores, adapted pricing, discounts and licensing
  • 2016-01-29 Reference designs for PTP OC/TC/HC/GM and PPS Master/Slave created for Altera's SoCkit and Xilinx Arty development boards, free demo donwloads will follow soon >> read more
  • 2016-01-10 PPS Master and Slave implemented and tested >> read more
  • 2015-10-14 NetTimeLogic succesfully tested OC/TC/HC at ISPCS2015 in Beijing >> read more
  • 2015-10-11 NetTimeLogic attended ISPCS2015 in Beijing
  • 2015-09-11 Flyers of PTP OC, TC and HC added.
  • 2015-09-10 NetTimeLogic will take part in the Industrial Day of the ISPCS >> read more
  • 2015-07-09 NetTimeLogic will take part in the ISPCS Plufest in Beijing to verify PTP cores. >> read more
  • 2015-06-11 NetTimeLogic is part of "Swiss Made Software". >> read more

Blog

<p>Visiting our partner Enclustra at Embedded World 2017</p>

Visiting our partner Enclustra at Embedded World 2017

Posted 14 weeks ago
<p>
RTC Master clock released allowing to store time to non-volatile memory and synchronize to RTCs. <a href="https://t.co/e3gzLJtzGn" title="http://www.nettimelogic.com/rtc-master.php">http://www.nettimelogic.com/rtc-master.php </a>

<br/></p>

RTC Master clock released allowing to store time to non-volatile memory and synchronize to RTCs. http://www.nettimelogic.com/rtc-master.php

Posted 24 weeks ago
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<p>Things are slowly getting ready</p>

Things are slowly getting ready

Posted 43 weeks ago
<p>Demosetup ready</p>

Demosetup ready

Posted 59 weeks ago
<p>Flightcase ready for a nice little demo setup</p>

Flightcase ready for a nice little demo setup

Posted 73 weeks ago
<p>Increased accuracy by >50% to +/-20ns with just some small tricks</p>

Increased accuracy by >50% to +/-20ns with just some small tricks

Posted 75 weeks ago
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<p>Just received two Xilinx Arty boards. They will be used for a reference design of NetTimeLogic’s small PTP OC slave only solution.</p>

Just received two Xilinx Arty boards. They will be used for a reference design of NetTimeLogic’s small PTP OC slave only solution.

Posted 76 weeks ago
<p>PI servo loop optimization => now < +/-50ns<br/></p>

PI servo loop optimization => now < +/-50ns

Posted 85 weeks ago
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NetTimeLogic on Tumblr

Just joined tumblr, another platform for news about NetTimeLogic’s development

Posted 92 weeks ago