DCF Slave

NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DCF signal encoded as PWM. The encoding scheme is the one of the DCF77 sender near Frankfurt, Germany. The whole encoding, algorithms and calculations are implemented in the core, no CPU is required. This allows running DCF synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

The DCF Slave Clock requires a PWM encoded DCF77 signal (see picture on the right), this can be purchased for under 20$ at e.g. Conrad

BLOCK DIAGRAM

Data Stream

Data Stream from DCF antenna with encoder aligned with synchronized PPS

FEATURES

  • DCF Slave Clock
  • Supports DCF-77 format
  • Optional Signal Filter
  • DCF decoding and time format conversion
  • DCF supervision
  • Input delay compensation
  • Air propagation delay compensation
  • Additional seconds correction to convert between UTC and TAI time (or any other time base)
  • Synchronization accuracy: +/- 10 ms
  • AXI4 Light register set or static configuration
  • Timestamp resolution with 50 MHz system clock: 20ns
  • Hardware PI Servo

Licensing & Pricing

There are different licensing possabilities. All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  2400$
  • Site Source Code: 4400$

DOWNLOADS

Evaluation binaries available for Digilent's Arty and Terasic's SoCKit develolopment boards or as Modelsim(R) precompiled libraries => contact us for free access

Dcf_Slave_Flyer.pdf Dcf_Slave_Flyer.pdf
Size : 268.112 Kb
Type : pdf
Dcf_Slave_ReferenceManual.pdf Dcf_Slave_ReferenceManual.pdf
Size : 1103.136 Kb
Type : pdf