NetTimeLogic provides two different PPS cores, a PPS Master and a PPS Slave.
All cores are in plain VHDL and completely FPGA vendor independent. The PPS processors are implemented as full hardware cores, no soft-core CPUs are used.
The PPS Master from NetTimeLogic is a full hardware only implementation of an PPS Master to distribute frequency and phase (within one second) via PPS.
The PPS Slave from NetTimeLogic is a full hardware only implementation of a PPS synchronizer. It allows to synchronize the local clock to a PPS input without the need of software or a soft-core CPU.