NetTimeLogic developed a PPS analyzer specifically for (PTP) Plugfests where multiple devices are synchronizing each other and the accuracy of the individual devices shall be measured via PPS (offset from reference PPS). The device has 8 PPS inputs that are measured simultaneously and it synchronizes itself to an additional reference PPS input. Additionaly it has a PPS output of the synchronized clock which is used for PPS measurement. Multiple PPS Analyzers can be connected to the same host and are all discovered automatically. It uses a serial interface (mostly over USB) to access the registers in the FPGA. In the FPGA it uses NetTimeLogic's configuration IP (free of charge) which represents an AXI Master to the other IP cores. It uses a proprietary protocol to convert the serial data stream from/to AXI register access. The core part consists of the following NetTimeLogic IP cores: PPS Slave IP core, PPS Master IP core, Adjustable Counter Clock IP core and mutiple instances of the Signal Timestamper IP core. The tool needs no configuration and self-discovers all cores available in the design. It allows to access all registers in the design (also third party) which are connected to the AXI bus.
The application is written with Qt as GUI framework and is currently available for Windows. The measured offsets are read by the PPS Analyzer application via UART and shown in a chart.
The hardware used for the PPS Analyzer consists of a custom PPS shield for the Arty board from Digilent
Grey: Reference PPS, Red: PPS from device under test, Others: not connected
This is a saved screen (you can save the current screens as PNG, TIFF or BMP) from the swiss PTP Plugfest 2017
- 8 PPS Inputs
- 1 Reference PPS Input
- 1 PPS Output
- Synchronized Clock via PPS
- Timestamp resolution 10ns
- PPS compensated for synchronization error introduced by the reference PPS
- Multiple Analyzers supported
- Selfdiscovery of all Analyzers
- Save screen as PNG, TIFF or BMP