IRIG Slave

NetTimeLogic’s IRIG SlaveClock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004/B124, B005/B125, B006/B126 and B007/B127 Master . The whole encoding, convertion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.

All calculations and corrections are implemented completely in HW.

Block Diagram


Synchronization Accuracy

100ns per division on osciloscope

The synchronization accuracy achieved witz a 50MHz oscilator is around +/-25ns


  • IRIG Slave Clock
  • Supports IRIG-B006/B126 format (compatible with B004/B124, B005/B125, B006/B126 and B007/B127 IRIG-B Masters)
  • IRIG decoding and time format conversion
  • IRIG supervision
  • Input delay compensation
  • Cable delay compensation
  • Additional seconds correction to convert between UTC and TAI time (or any other time base)
  • Synchronization accuracy: +/- 25ns
  • AXI4 Light register set or static configuration
  • Timestamp resolution with 50 MHz system clock: 20ns
  • Hardware PI Servo

Licensing & Pricing

There are different licensing possabilities. All prices are in US Dollars without VAT, all prices are one-time fees, no royalties apply:

  • Project Source Code:  2700$
  • Site Source Code: 4900$


Evaluation binaries available for Digilent's Arty and Terasic's SoCKit develolopment boards or as Modelsim(R) precompiled libraries => contact us for free access

Irig_Slave_Flyer.pdf Irig_Slave_Flyer.pdf
Size : 264.46 Kb
Type : pdf
Irig_Slave_ReferenceManual.pdf Irig_Slave_ReferenceManual.pdf
Size : 938.132 Kb
Type : pdf