Sven Meier
Managing Director & FPGA Design Engineer
Sven Meier has a bachelor degree in information technology and a master of advanced studies degree in business information technology from the Zürich University of Applied Sciences (Switzerland).
Sven is the Managing Director and lead FPGA Design Engineer at NetTimeLogic.
In 2015 he founded NetTimeLogic GmbH with the goal to develop best in class FPGA Ip cores which can be integrated as kind of co-processors handling the different protocols directly in hardware.
He has in-depth knowledge in time synchronization, realtime ethernet, software and FPGA development as well as embedded Linux. Over the last years he developed several FPGA IP cores for time synchronization protocols such as PTP, IRIG-B and PPS or realtime Ethernet protocols like Profinet, Ethernet Powerlink and Time Sensitive Networking (TSN). He also implemented Ethernet redundancy protocol cores for PRP and HSR as part of the standardization of those protocols.
Sven Meier is part of the standardization group for IEEE1588 and ISPCS committee and created several papers/publications/articels/webinars in this area:
- Wireless IEEE 1588 over an infrared interface
- IEEE 1588 applied in the environment of high availability LANs
- IEEE 1588 syntonization and synchronization functions completely realized in hardware
- Teil 7 der TSN-Serie - Die Zeitsynchronisation
- Time Card and Open Time Server
Several patents are referring to publications from Sven Meier:
- EP2680466A1
- EP2367309A1
- EP2296318A1
- EP2712099A1
- EP2518634A1
- EP2712100A1
- EP2568673A1
- EP2695340A1
- EP2015501A1
- US20110135047
- WO2012007276A1
- WO2011070616A1
- WO2011077558A1
- WO2014044501A1
- WO2011098466A1
- WO2014044502A1
- WO2012168262A1
- WO2009007228A1
He also developed some Wireshark dissectors for PRP.
Read an interview with Sven Meier by HardwareBee.
E-Mail: sven.meier(at)nettimelogic.com