Sven Meier

Managing Director & FPGA Design Engineer

Sven Meier has a bacherlor degree in information technology and a master of advanced studies degree in business information technology from the Zürich University of Applied Sciences (Switzerland).

He has in-depth knowledge in time synchronization, realtime ethernet and FPGA development. Over the last 10 years he developed several FPGA IP cores for time synchronization protocols such as PTP, IRIG-B and PPS or realtime Ethernet protocols like Profinet and Ethernet Powerlink. He also implemented Ethernet redundancy protocol cores for PRP and HSR as part of the standardization of those protocols.

Sven Meier is part of the standardization group for IEEE1588 and created several papers in this area:

Several patents are refering to publications from Sven Meier:

He also developed some Wireshark dissectors for PRP.